Archive for September 30th, 2008
XMOS has introduced it’s XS1-G4 multicore processor.
The XMOS architecture combines a number of processing cores, each with its own memory and I/O system, on a single chip. The processing cores are general-purpose in the sense that they can execute languages such as C; they also have direct support for concurrent processing (multi-threading), communication and I/O.
A high-performance switch supports communication between the processors, and inter-chip XLinks are provided so that systems can easily be constructed from multiple chips. Any thread can communicate with any other thread in the system using single-cycle communication instructions. The system switches can efficiently route short packets or streamed data.
The XMOS architecture makes it practical to use software to perform many functions that traditionally have been implemented in hardware, for example interfaces and I/O controllers. Both input and output operations can be timed to a local clock or an externally provided clock. The architecture is both multithreaded and event-driven. Threads can be used to define independent tasks; the event mechanism enables fast and controlled responses to a multitude of signals.
The architecture is designed to support any programming language, such as C. The full benefits of the instruction set may require extensions to standard languages, libraries, or the use of assembly language. We have designed XC, a version of C that supports I/O, multi-core and precision timing.
Each XS1-G XCore executes up to eight threads concurrently, at a speed of up to 400 MIPS. A thread has a dedicated register set enabling it to operate as a logical core. The 8 threads share a single 64 KByte unified memory with no access collisions. Integer and fixed point operations are provided for efficient DSP and cryptographic operations.
Each XS1-G XCore has 64 I/O pins that are programmed from software. Thread execution is deterministic and hence each thread can implement a hard real-time I/O task, regardless of the behaviour of other threads. I/O pins are grouped into logical ports of width 1, 4, 8, 16 and 32 bits. Each port incorporates serialisation/deserialisation, synchronisation with the external interface, and precision timing. Each XCore incorporates eight timers that measure time relative to a 100 MHz reference clock.
Each XS1-G XCore is connected to a switch via four internal links. Each link is capable of transferring data at 800 Mbits/second. The switch provides full connectivity between the cores on the chip, and also provides up to sixteen external XLinks. Each XLink is capable of transferring data at up to 400 Mbits/second.
Sounds fast! And XC is a C-like language that provides full support for the parallel architecture, so the time to get up to speed using these parts should be reduced.
There are currently two evaluation boards available, the $99 XC-1 card, and the $999 XS1-G development kit (ouch!).
To me, it looks like they are like a Parallax Propeller Chip on serious steroids. If they’re cost effective, it might just make the Propeller stop turning.
[XMOS]
IntellaSys has introduced an interesting looking part called the 40C18. The 40C18 has 40 cores on a single chip, with the cores arranged in a 4 x 10 pattern. Some cores have I/O, such as digital I/O pins, analog inputs and outputs, or interface to external memory, while other cores are purely computational. IntellaSys claims that the combined cores can deliver up to 26 billion operations per second.
Each core has 32 instructions, where each instruction is 5 bits. There are 64 words of RAM and 64 words of ROM per core, with each word being 18 bits. Words are divided into slots, for a total of 4 slots per word, with slot 3 being a ’short slot’. It appears that this would allow at least 192 instructions, plus however the short slots are used.
The next is straight from the data sheet and says it better than I could:
Each core runs asynchronously, at the full native speed of the silicon. During interprocessor communication, synchronization happens automatically; the programmer does not have to create synchronization methods. Adjacent cores communicate through dedicated ports. A core waiting for data from a neighbor goes to sleep, dissipating less than one microwatt. Likewise, a core sending data to a neighbor not ready to receive it goes to sleep until that neighbor accepts it.
A wake up occurs almost instantly, upon the rising edge of the synchronizing signal. With the wake up logic controlling power use, there is no need for complex power control strategies. Power is conserved as a natural consequence of good program design. External I/O signals may also be used to wake up sleeping processors. The small size and low power make the SEAforth 40C18 a good value both in terms of MIPS per dollar and MIPS per milliwatt.
I/O ports on the SEAforth 40C18 are highly configurable because they are controlled by firmware. The 4-wire SPI port, the 2-wire serial ports, and the single-bit GPIO ports can be programmed to perform a large variety of functions. With the available processing power, wireless solutions become possible without the need for separate wireless chips. Ports can be programmed to support I2C, I2S, asynchronous serial, or synchronous serial ports. Serial ports can also be used to connect multiple SEAforth 40C18s.
In addition to serial I/O, two nodes have two dedicated parallel I/O ports. These can be used for parallel I/O, or when combined, can drive an external memory device.
It’s an interesting looking part, provided your application can benefit from small processes with a high degree of parallelism. DSP applications naturally come to mind, along with other small specialized control functions.
While most of my uses couldn’t take advantage of such an device, it runs Forth, so that makes it intrinsically cool. Check out the web page for development tools, the data sheets, and also the forthDrive processor, which is a 24 core version of the 40C18.
From LowComDom:
In a large crock pot:
Combine 1 pound of all purpose fear, a pinch of 9/11 and dollop of fake homeland security.
Combine tax cuts for the wealthy, exclusive Halliburton contracts, oil profits and corporate welfare til smooth, then add to the mix.
Coarsely chop off social programs for the poor, strain Social Security through private cheesecloth and then drain and discard unnecessary excess minorities.
In a separate pot, bring bigotry, gay bashing and pro-birth rhetoric to a boil. Stir in right-wing religious zealots and the elimination of the Separation of Church and State. Bring to boil again and then generously pour into the mix.
Stir in secrecy, fraud, corruption and criminal negligence. If desired, mash fixed intelligence with a treason masher and sprinkle with super secret background.
Add Swift Boat smear tactics to taste and garnish with language manipulation (from secret playbook).
Put a lid on it and go on vacation.
Danger: Do not lift cover. It may explode in your face.