DM6446 Register Addresses

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Todo

  • Add DDR2 control registers from SPRUE22C, page 39
  • Add missing USB registers (maybe)
  • Fix 'To be done' entries

Technical Documents

Memory Map Summary

SPRS283F, page 20
Start End Size ARM/EDMA C64x+
0x00000000 0x00001fff 8K ARM RAM0 (Instruction) Reserved
0x00002000 0x00003fff 8K ARM RAM1 (Instruction)
0x00004000 0x00005fff 8K ARM ROM (Instruction)
0x00006000 0x00007fff 8K Reserved
0x00008000 0x00009fff 8K ARM RAM0 (Data)
0x0000a000 0x0000bfff 8K ARM RAM1 (Data)
0x0000c000 0x0000dfff 8K ARM ROM (Data)
0x0000e000 0x0000ffff 8K Reserved
0x00010000 0x000fffff 960K
0x00100000 0x001fffff 1M VICP
0x00200000 0x007fffff 6M Reserved
0x00800000 0x0080ffff 64K L2 RAM/Cache
0x00810000 0x00e07fff 6112K Reserved
0x00e08000 0x00e0ffff 32K L1P Cache
0x00e10000 0x00f03fff 976K Reserved
0x00f04000 0x00f0ffff 48K L1D RAM
0x00f10000 0x00f17fff 32K L1D Cache
0x00f18000 0x017fffff 9120K Reserved
0x01800000 0x01bbffff 3840K CFG Space
0x01bc0000 0x01bc0fff 4K ARM ETB Memory
0x01bc1000 0x01bc17ff 2K ARM ETB Registers CFG Space
0x01bc1800 0x01bc18ff 256 ARM IceCrusher
0x01bc1900 0x01bfffff 255744 Reserved
0x01c00000 0x01ffffff 4M CFG Bus Peripherals CFG Bus Peripherals
0x02000000 0x09ffffff 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data)
0x0a000000 0x0bffffff 32M Reserved Reserved
0x0c000000 0x0fffffff 64M VLYNQ (Remote)
0x10000000 0x10007fff 32K Reserved
0x10008000 0x10009fff 8K ARM RAM0
0x1000a000 0x1000bfff 8K ARM RAM1
0x1000c000 0x1000dfff 8K ARM ROM
0x1000e000 0x1000ffff 8K Reserved
0x10010000 0x110fffff 17344K
0x11100000 0x111fffff 1M
0x11200000 0x117fffff 6M
0x11800000 0x1180ffff 64K L2 RAM/Cache L2 RAM/Cache
0x11810000 0x11e07fff 6112K Reserved Reserved
0x11e08000 0x11e0ffff 32K L1P Cache L1P Cache
0x11e10000 0x11f03fff 976K Reserved Reserved
0x11f04000 0x11f0ffff 48K L1D RAM L1D RAM
0x11f10000 0x11f17fff 32K L1D RAM/Cache L1D RAM/Cache
0x11f18000 0x1fffffff 241M-32K Reserved Reserved
0x20000000 0x20007fff 32K DDR2 Control Registers DDR2 Control Registers
0x20008000 0x41ffffff 544M-32k Reserved Reserved
0x42000000 0x4fffffff 224M Reserved EMIFA/VLYNQ Shadow
0x50000000 0x7fffffff 768M Reserved Reserved
0x80000000 0x8fffffff 256M DDR2 DDR2
0x90000000 0xffffffff 1792M Reserved Reserved

Configuration Memory Map Summary

SPRS283F, page 21
Start End Size ARM/EDMA C64x+
0x01800000 0x0180ffff 64K Reserved C64x+ Interrupt Controller
0x01810000 0x01800fff 4K C64x+ Powerdown Controller
0x01811000 0x01811fff 4K C64x+ Security ID
0x01812000 0x01812fff 4K C64x+ Revision ID
0x01820000 0x0182ffff 64K C64x+ EMC
0x01830000 0x0183ffff 64K Reserved
0x01840000 0x0184ffff 64K C64x+ Memory System
0x01850000 0x0187ffff 192K Reserved
0x01880000 0x01bbffff 3328K Reserved
0x01bc0000 0x01bc00ff 256 ARM ETB Memory Reserved
0x01bc0100 0x01bc01ff 256 Pin Manager And Trace
0x01bc0200 0x01bc0fff 3.5K Reserved
0x01bc1000 0x01bc17ff 2K ARM ETB Registers
0x01bc1800 0x01bc18ff 256 ARM Ice Crusher
0x01bc1900 0x01bfffff 255744 Reserved
0x01c00000 0x01c0ffff 64K EDMA CC EDMA CC
0x01c10000 0x01c103ff 1K EDMA TC0 EDMA TC0
0x01c10400 0x01c107ff 1K EDCMA TC1 EDCMA TC1
0x01c18800 0x01c19fff 6K Reserved Reserved
0x01c1a000 0x01c1ffff 24K
0x01c20000 0x01c203ff 1K UART0
0x01c20400 0x01c207ff 1K UART1
0x01c20800 0x01c20bff 1K UART2
0x01c20c00 0x01c20fff 1K Reserved
0x01c21000 0x01c213ff 1K I2C
0x01c21400 0x01c217ff 1K Timer0 Timer0
0x01c21800 0x01c21bff 1K Timer1 Timer1
0x01c21c00 0x01c21fff 1K Timer2 (Watchdog) Reserved
0x01c22000 0x01c223ff 1K PWM0
0x01c22400 0x01c227ff 1K PWM1
0x01c22800 0x01c22bff 1K PWM2
0x01c22c00 0x01c3ffff 117K Reserved
0x01c40000 0x01c407ff 2K System Module System Module
0x01c40800 0x01c40bff 1K PLL1 Reserved
0x01c40c00 0x01c40fff 1K PLL2
0x01c41000 0x01c41fff 4K PSC PSC
0x01c42000 0x01c4202f 48 Reserved Reserved
0x01c42030 0x01c42033 4 DDR2 VTP Reg DDR2 VTP Reg
0x01c42034 0x01c423ff 1K - 52 Reserved Reserved
0x01c42400 0x01c47fff 23K
0x01c48000 0x01c483ff 1K INTC
0x01c48400 0x01c5ffff 95K Reserved
0x01c60000 0x01c63fff 16K
0x01c64000 0x01c65fff 8K USB
0x01c66000 0x01c667ff 2K ATA/CF
0x01c66800 0x01c66fff 2K SPI
0x01c67000 0x01c677ff 2K GPIO
0x01c67800 0x01c67fff 2K HPI HPI
0x01c68000 0x01c6ffff 32K Reserved Reserved
0x01c70000 0x01c73fff 16K VPSS
0x01c74000 0x01c7ffff 48K Reserved
0x01c80000 0x01c80fff 4K EMAC
0x01c81000 0x01c81fff 4K EMAC CMR
0x01c82000 0x01c83fff 8K EMAC Control Module RAM
0x01c84000 0x01c847ff 2K MDIO
0x01c84800 0x01c84fff 2K Reserved
0x01c85000 0x01cbffff 236K
0x01cc0000 0x01cdffff 128K VICP VICP
0x01ce0000 0x01cfffff 128K Reserved Reserved
0x01d00000 0x01dfffff 1M
0x01e00000 0x01e00fff 4K EMIFA
0x01e01000 0x01e01fff 4K VLYNQ
0x01e02000 0x01e03fff 8K ASP ASP
0x01e04000 0x01e0ffff 48K Reserved Reserved
0x01e10000 0x01e1ffff 64K MMC/SD/SDIO
0x01e20000 0x01e3ffff 128K Reserved
0x01e40000 0x01ffffff 1792K
0x02000000 0x03ffffff 32M EMIFA Data/Code (CS2) EMIFA Data (CS2)
0x04000000 0x05ffffff 32M EMIFA Data/Code (CS3) EMIFA Data (CS3)
0x06000000 0x07ffffff 32M EMIFA Data/Code (CS4) EMIFA Data (CS4)
0x08000000 0x09ffffff 32M EMIFA Data/Code (CS5) EMIFA Data (CS5)
0x0a000000 0x0bffffff 32M Reserved Reserved
0x0c000000 0x0fffffff 64M VLYNQ (Remote)

EDMA CC

  • (To be done)

EDMA TC0

  • (To be done)

EDMA TC1

  • (To be done)

UART0

SPRUE33A, page 21
Address Acronym Description Section
0x01c20000 RBR Receiver Buffer Register (read only) Section 3.1
0x01c20000 THR Transmitter Holding Register (write only) Section 3.2
0x01c20004 IER Interrupt Enable Register Section 3.3
0x01c20008 IIR Interrupt Identification Register (read only) Section 3.4
0x01c20008 FCR FIFO Control Register (write only) Section 3.5
0x01c2000c LCR Line Control Register Section 3.6
0x01c20010 MCR Modem Control Register Section 3.7
0x01c20014 LSR Line Status Register Section 3.8
0x01c20020 DLL Divisor LSB Latch Section 3.9
0x01c20024 DLH Divisor MSB Latch Section 3.9
0x01c20028 PID1 Peripheral Identification Register 1 Section 3.10
0x01c2002c PID2 Peripheral Identification Register 2 Section 3.10
0x01c20030 PWREMU_MGMT Power and Emulation Management Register Section 3.11

UART1

SPRUE33A, page 21
Address Acronym Description Section
0x01c20400 RBR Receiver Buffer Register (read only) Section 3.1
0x01c20400 THR Transmitter Holding Register (write only) Section 3.2
0x01c20404 IER Interrupt Enable Register Section 3.3
0x01c20408 IIR Interrupt Identification Register (read only) Section 3.4
0x01c20408 FCR FIFO Control Register (write only) Section 3.5
0x01c2040c LCR Line Control Register Section 3.6
0x01c20410 MCR Modem Control Register Section 3.7
0x01c20414 LSR Line Status Register Section 3.8
0x01c20420 DLL Divisor LSB Latch Section 3.9
0x01c20424 DLH Divisor MSB Latch Section 3.9
0x01c20428 PID1 Peripheral Identification Register 1 Section 3.10
0x01c2042c PID2 Peripheral Identification Register 2 Section 3.10
0x01c20430 PWREMU_MGMT Power and Emulation Management Register Section 3.11

UART2

SPRUE33A, page 21
Address Acronym Description Section
0x01c20800 RBR Receiver Buffer Register (read only) Section 3.1
0x01c20800 THR Transmitter Holding Register (write only) Section 3.2
0x01c20804 IER Interrupt Enable Register Section 3.3
0x01c20808 IIR Interrupt Identification Register (read only) Section 3.4
0x01c20808 FCR FIFO Control Register (write only) Section 3.5
0x01c2080c LCR Line Control Register Section 3.6
0x01c20810 MCR Modem Control Register Section 3.7
0x01c20814 LSR Line Status Register Section 3.8
0x01c20820 DLL Divisor LSB Latch Section 3.9
0x01c20824 DLH Divisor MSB Latch Section 3.9
0x01c20828 PID1 Peripheral Identification Register 1 Section 3.10
0x01c2082c PID2 Peripheral Identification Register 2 Section 3.10
0x01c20830 PWREMU_MGMT Power and Emulation Management Register Section 3.11

I2C

SPRUE27D, page 23
Address Acronym Description Section
0x01c21000 ICOAR I2C Own Address Register Section 3.1
0x01c21004 ICIMR I2C Interrupt Mask Register Section 3.2
0x01c21008 ICSTR I2C Interrupt Status Register Section 3.3
0x01c2100c ICCLKL I2C Clock Low-Time Divider Register Section 3.4
0x01c21010 ICCLKH I2C Clock High-Time Divider Register Section 3.4
0x01c21014 ICCNT I2C Data Count Register Section 3.5
0x01c21018 ICDRR I2C Data Receive Register Section 3.6
0x01c2101c ICSAR I2C Slave Address Register Section 3.7
0x01c21020 ICDXR I2C Data Transmit Register Section 3.8
0x01c21024 ICMDR I2C Mode Register Section 3.9
0x01c21028 ICIVR I2C Interrupt Vector Register Section 3.10
0x01c2102c ICEMDR I2C Extended Mode Register Section 3.11
0x01c21030 ICPSC I2C Prescaler Register Section 3.12
0x01c21034 ICPID1 I2C Peripheral Identification Register 1 Section 3.13
0x01c21038 ICPID2 I2C Peripheral Identification Register 2 Section 3.13

Timer0

SPRUE26, page 22
Address Acronym Description Section
0x01c21400 PID12 Peripheral Identification Register 12 Section 9.1
0x01c21404 EMUMGT Emulation Management Register Section 9.2
0x01c21410 TIM12 Timer Counter Register 12 Section 9.3
0x01c21414 TIM34 Timer Counter Register 34 Section 9.3
0x01c21418 PRD12 Timer Period Register 12 Section 9.4
0x01c2141c PRD34 Timer Period Register 34 Section 9.4
0x01c21420 TCR Timer Control Register Section 9.5
0x01c21424 TGCR Timer Global Control Register Section 9.6
0x01c21428 WDTCR Watchdog Timer Control Register Section 9.7

Timer1

SPRUE26, page 22
Address Acronym Description Section
0x01c21800 PID12 Peripheral Identification Register 12 Section 9.1
0x01c21804 EMUMGT Emulation Management Register Section 9.2
0x01c21810 TIM12 Timer Counter Register 12 Section 9.3
0x01c21814 TIM34 Timer Counter Register 34 Section 9.3
0x01c21818 PRD12 Timer Period Register 12 Section 9.4
0x01c2181c PRD34 Timer Period Register 34 Section 9.4
0x01c21820 TCR Timer Control Register Section 9.5
0x01c21824 TGCR Timer Global Control Register Section 9.6
0x01c21828 WDTCR Watchdog Timer Control Register Section 9.7

Timer2

SPRUE26, page 22
Address Acronym Description Section
0x01c21c00 PID12 Peripheral Identification Register 12 Section 9.1
0x01c21c04 EMUMGT Emulation Management Register Section 9.2
0x01c21c10 TIM12 Timer Counter Register 12 Section 9.3
0x01c21c14 TIM34 Timer Counter Register 34 Section 9.3
0x01c21c18 PRD12 Timer Period Register 12 Section 9.4
0x01c21c1c PRD34 Timer Period Register 34 Section 9.4
0x01c21c20 TCR Timer Control Register Section 9.5
0x01c21c24 TGCR Timer Global Control Register Section 9.6
0x01c21c28 WDTCR Watchdog Timer Control Register Section 9.7

PWM0

SPRUE31, page 12
Address Acronym Description Section
0x01c22000 PID PWM Peripheral Identification Register Section 3.1
0x01c22004 PCR PWM Peripheral Control Register Section 3.2
0x01c22008 CFG PWM Configuration Register Section 3.3
0x01c2200c START PWM Start Register Section 3.4
0x01c22010 RPT PWM Repeat Count Register Section 3.5
0x01c22014 PER PWM Period Register Section 3.6
0x01c22018 PH1D PWM First-Phase Duration Register Section 3.7

PWM1

SPRUE31, page 12
Address Acronym Description Section
0x01c22400 PID PWM Peripheral Identification Register Section 3.1
0x01c22404 PCR PWM Peripheral Control Register Section 3.2
0x01c22408 CFG PWM Configuration Register Section 3.3
0x01c2240c START PWM Start Register Section 3.4
0x01c22410 RPT PWM Repeat Count Register Section 3.5
0x01c22414 PER PWM Period Register Section 3.6
0x01c22418 PH1D PWM First-Phase Duration Register Section 3.7

PWM2

SPRUE31, page 12
Address Acronym Description Section
0x01c22800 PID PWM Peripheral Identification Register Section 3.1
0x01c22804 PCR PWM Peripheral Control Register Section 3.2
0x01c22808 CFG PWM Configuration Register Section 3.3
0x01c2280c START PWM Start Register Section 3.4
0x01c22810 RPT PWM Repeat Count Register Section 3.5
0x01c22814 PER PWM Period Register Section 3.6
0x01c22818 PH1D PWM First-Phase Duration Register Section 3.7

System Module Registers

SPRS283F, page 62
Address Acronym Description Section
0x01c40000 PINMUX0 Pin multiplexing control 0 Section 3.5.4
0x01c40004 PINMUX1 Pin multiplexing control 1 Section 3.5.5
0x01c40008 DSPBOOTADDR Boot address of DSP Section 3.3.1.2
0x01c4000c SUSPSRC Emulator Suspend Source Section 3.6
0x01c40010 INTGEN ARM/DSP Interrupt Status and Control Section 6.7.3
0x01c40014 BOOTCFG Device boot configuration Section 3.3.1.1
0x01c40018 Reserved
0x01c4001c
0x01c40020
0x01c40024
0x01c40028 JTAGID JTAGID/Device ID number Section 6.25.1
0x01c4002c Reserved
0x01c40030 HPI_CTL HPI control Section 3.5.6.10
0x01c40034 USBPHY_CTL USB PHY control Section 6.15.1
0x01c40038 CHP_SHRTSW Chip shorting switch control Section 3.2.1
0x01c4003c MSTPRI0 Bus master priority control 0 Section 3.5.1
0x01c40040 MSTPRI1 Bus master priority control 1 Section 3.5.1
0x01c40044 VPSS_CLKCTL VPSS clock control
0x01c40048 VDD3P3V_PWDN VDD 3.3V I/O powerdown control Section 3.2.2
0x01c4004c DRRVTPER Enables access to the DDR2 VTP Register
0x01c40050 Reserved
0x01c40054
0x01c40058
0x01c4005c
0x01c40060
0x01c40064
0x01c40068
0x01c4006c

PLL1

SPRUE14B, page 103
Address Acronym Register Description Section
0x01c40800 PID Peripheral ID Register Section 6.4.1
0x01c40804 Reserved
0x01c40808
0x01c4080c
0x01c40810
0x01c40814
0x01c40818
0x01c4081c
0x01c40820
0x01c40824
0x01c40828
0x01c4082c
0x01c40830
0x01c40834
0x01c40838
0x01c4083c
0x01c40840
0x01c40844
0x01c40848
0x01c4084c
0x01c40850
0x01c40854
0x01c40858
0x01c4085c
0x01c40860
0x01c40864
0x01c40868
0x01c4086c
0x01c40870
0x01c40874
0x01c40878
0x01c4087c
0x01c40880
0x01c40884
0x01c40888
0x01c4088c
0x01c40890
0x01c40894
0x01c40898
0x01c4089c
0x01c408a0
0x01c408a4
0x01c408a8
0x01c408ac
0x01c408b0
0x01c408b4
0x01c408b8
0x01c408bc
0x01c408c0
0x01c408c4
0x01c408c8
0x01c408cc
0x01c408d0
0x01c408d4
0x01c408d8
0x01c408dc
0x01c408e0
0x01c408e4 RSTYPE Reset Type Status Register Section 6.4.2
0x01c408e8 Reserved
0x01c408ec
0x01c408f0
0x01c408f4
0x01c408f8
0x01c408fc
0x01c40900 PLLCTL PLL Control Register Section 6.4.3
0x01c40910 PLLM PLL Multiplier Control Register Section 6.4.4
0x01c40918 PLLDIV1 PLL Controller Divider 1 Register Section 6.4.5
0x01c4091c PLLDIV2 PLL Controller Divider 2 Register Section 6.4.6
0x01c40920 PLLDIV3 PLL Controller Divider 3 Register Section 6.4.7
0x01c40928 POSTDIV PLL Post-Divider Control Register Section 6.4.8
0x01c4092c BPDIV Bypass Divider Register Section 6.4.9
0x01c40930 Reserved
0x01c40934
0x01c40938 PLLCMD PLL Controller Command Register Section 6.4.10
0x01c4093c PLLSTAT PLL Controller Status Register Section 6.4.11
0x01c40940 ALNCTL PLL Controller Clock Align Control Register Section 6.4.12
0x01c40944 DCHANGE PLLDIV Ratio Change Status Register Section 6.4.13
0x01c40948 CKEN Clock Enable Control Register Section 6.4.14
0x01c4094c CKSTAT Clock Status Register Section 6.4.15
0x01c40950 SYSTAT SYSCLK Status Register Section 6.4.16
0x01c40954 Reserved
0x01c40958
0x01c4095c
0x01c40960
0x01c40964 PLLDIV5 PLL Controller Divider 5 Register Section 6.4.17

PLL2

SPRUE14B, page 103
Address Acronym Register Description Section
0x01c40c00 PID Peripheral ID Register Section 6.4.1
0x01c40c04 Reserved
0x01c40c08
0x01c40c0c
0x01c40c10
0x01c40c14
0x01c40c18
0x01c40c1c
0x01c40c20
0x01c40c24
0x01c40c28
0x01c40c2c
0x01c40c30
0x01c40c34
0x01c40c38
0x01c40c3c
0x01c40c40
0x01c40c44
0x01c40c48
0x01c40c4c
0x01c40c50
0x01c40c54
0x01c40c58
0x01c40c5c
0x01c40c60
0x01c40c64
0x01c40c68
0x01c40c6c
0x01c40c70
0x01c40c74
0x01c40c78
0x01c40c7c
0x01c40c80
0x01c40c84
0x01c40c88
0x01c40c8c
0x01c40c90
0x01c40c94
0x01c40c98
0x01c40c9c
0x01c40ca0
0x01c40ca4
0x01c40ca8
0x01c40cac
0x01c40cb0
0x01c40cb4
0x01c40cb8
0x01c40cbc
0x01c40cc0
0x01c40cc4
0x01c40cc8
0x01c40ccc
0x01c40cd0
0x01c40cd4
0x01c40cd8
0x01c40cdc
0x01c40ce0
0x01c40ce4 RSTYPE Reset Type Status Register Section 6.4.2
0x01c40ce8 Reserved
0x01c40cec
0x01c40cf0
0x01c40cf4
0x01c40cf8
0x01c40cfc
0x01c40d00 PLLCTL PLL Control Register Section 6.4.3
0x01c40d10 PLLM PLL Multiplier Control Register Section 6.4.4
0x01c40d18 PLLDIV1 PLL Controller Divider 1 Register Section 6.4.5
0x01c40d1c PLLDIV2 PLL Controller Divider 2 Register Section 6.4.6
0x01c40d20 PLLDIV3 PLL Controller Divider 3 Register Section 6.4.7
0x01c40d28 POSTDIV PLL Post-Divider Control Register Section 6.4.8
0x01c40d2c BPDIV Bypass Divider Register Section 6.4.9
0x01c40d30 Reserved
0x01c40d34
0x01c40d38 PLLCMD PLL Controller Command Register Section 6.4.10
0x01c40d3c PLLSTAT PLL Controller Status Register Section 6.4.11
0x01c40d40 ALNCTL PLL Controller Clock Align Control Register Section 6.4.12
0x01c40d44 DCHANGE PLLDIV Ratio Change Status Register Section 6.4.13
0x01c40d48 CKEN Clock Enable Control Register Section 6.4.14
0x01c40d4c CKSTAT Clock Status Register Section 6.4.15
0x01c40d50 SYSTAT SYSCLK Status Register Section 6.4.16
0x01c40d54 Reserved
0x01c40d58
0x01c40d5c
0x01c40d60
0x01c40d64 PLLDIV5 PLL Controller Divider 5 Register Section 6.4.17

PSC

SPRUE14B, page 79
Address Acronym Register Description Section
0x01c41000 PID Peripheral Revision and Class Information Register Section 7.7.1
0x01c41018 INTEVAL Interrupt Evaluation Register Section 7.7.2
0x01c41040 MERRPR0 Module Error Pending Register 0 (module 0-31) Section 7.7.3
0x01c41044 MERRPR1 Module Error Pending Register 1 (module 32-63) Section 7.7.4
0x01c41050 MERRCR0 Module Error Clear Register 0 (module 0-31) Section 7.7.5
0x01c41054 MERRCR1 Module Error Clear Register 1 (module 32-63) Section 7.7.6
0x01c41060 PERRPR Power Error Pending Register Section 7.7.7
0x01c41068 PERRCR Power Error Clear Register Section 7.7.8
0x01c41070 EPCPR External Power Error Pending Register Section 7.7.9
0x01c41078 EPCCR External Power Control Clear Register Section 7.7.10
0x01c41120 PTCMD Power Domain Transition Command Register Section 7.7.11
0x01c41128 PTSTAT Power Domain Transition Status Register Section 7.7.12
0x01c41200 PDSTATn Power Domain Status n Register Section 7.7.13
0x01c41300 PDCTLn Power Domain Control n Register Section 7.7.14
0x01c41800 MDSTATn Module Status n Register (modules 0-40) Section 7.7.15
0x01c41a00 MDCTLn Module Control n Register (modules 0-40) Section 7.7.16

INTC

SPRUE14B, page 103
Address Acronym Register Description Section
0x01c48000 FIQ0 Fast Interrupt Request Status Register 0 Section 9.4.1
0x01c48004 FIQ1 Fast Interrupt Request Status Register 1 Section 9.4.2
0x01c48008 IRQ0 Interrupt Request Status Register 0 Section 9.4.3
0x01c4800c IRQ1 Interrupt Request Status Register 1 Section 9.4.4
0x01c48010 FIQENTRY Fast Interrupt Request Entry Address Register Section 9.4.5
0x01c48014 IRQENTRY Interrupt Request Entry Address Register Section 9.4.6
0x01c48018 EINT0 Interrupt Enable Register 0 Section 9.4.7
0x01c4801c EINT1 Interrupt Enable Register 1 Section 9.4.8
0x01c48020 INTCTL Interrupt Operation Control Register Section 9.4.9
0x01c48024 EABASE Interrupt Entry Table Base Address Register Section 9.4.10
0x01c48028 Reserved
0x01c4802c
0x01c48030 INTPRI0 Interrupt 0-7 Priority Register 0 Section 9.4.11
0x01c48034 INTPRI1 Interrupt 8-15 Priority Register 1 Section 9.4.12
0x01c48038 INTPRI2 Interrupt 16-23 Priority Register 2 Section 9.4.13
0x01c4803c INTPRI3 Interrupt 24-31 Priority Register 3 Section 9.4.14
0x01c48040 INTPRI4 Interrupt 32-39 Priority Register 4 Section 9.4.15
0x01c48044 INTPRI5 Interrupt 40-47 Priority Register 5 Section 9.4.16
0x01c48048 INTPRI6 Interrupt 48-55 Priority Register 6 Section 9.4.17
0x01c4804c INTPRI7 Interrupt 56-63 Priority Register 7 Section 9.4.18

USB

SPRUE35E, page 73
Address Acronym Register Description Section
0x01c64000 Reserved
0x01c64004 CTRLR Control Register Section 4.1
0x01c64008 STATR Status Register Section 4.2
0x01c6400c Reserved
0x01c64010 RNDISR RNDIS Register Section 4.3
0x01c64014 AUTOREQ Autorequest Register Section 4.4
0x01c64018 Reserved
0x01c6401c
0x01c64020 INTSRCR USB Interrupt Source Register Section 4.5
0x01c64024 INTSETR USB Interrupt Source Set Register Section 4.6
0x01c64028 INTCLRR USB Interrupt Source Clear Register Section 4.7
0x01c6402c INTMSKR USB Interrupt Mask Register Section 4.8
0x01c64030 INTMSKSETR USB Interrupt Mask Set Register Section 4.9
0x01c64034 INTMSKCLRR USB Interrupt Mask Clear Register Section 4.10
0x01c64038 INTMASKEDR USB Interrupt Source Masked Register Section 4.11
0x01c6403c EOIR USB End of Interrupt Register Section 4.12
0x01c64040 INTVECTR USB Interrupt Vector Register Section 4.13
0x01c64044 Reserved
0x01c64048
0x01c6404c
0x01c64050
0x01c64054
0x01c64058
0x01c6405c
0x01c64060
0x01c64064
0x01c64068
0x01c6406c
0x01c64070
0x01c64074
0x01c64078
0x01c6407c
0x01c64080 TCPPICR Transmit CPPI Control Register Section 4.14
0x01c64084 TCPPITDR Transmit CPPI Teardown Register Section 4.15
0x01c64088 CPPIEOIR CPPI DMA End of Interrupt Register Section 4.16
0x01c6408c Reserved
0x01c64090 TCPPIMSKSR Transmit CPPI Masked Status Register Section 4.17
0x01c64094 TCPPIRAWSR Transmit CPPI Raw Status Register Section 4.18
0x01c64098 TCPPIIENSETR Transmit CPPI Interrupt Enable Set Register Section 4.19
0x01c6409c TCPPIIENCLRR Transmit CPPI Interrupt Enable Clear Register Section 4.20
0x01c640a0 Reserved
0x01c640a4
0x01c640a8
0x01c640ac
0x01c640b0
0x01c640b4
0x01c640b8
0x01c640bc
0x01c640c0 RCPPICR Receive CPPI Control Register Section 4.21
0x01c640c4 Reserved
0x01c640c8
0x01c640cc
0x01c640d0 RCPPIMSKSR Receive CPPI Masked Status Register Section 4.22
0x01c640d4 RCPPIRAWSR Receive CPPI Raw Status Register Section 4.23
0x01c640d8 RCPPIENSETR Receive CPPI Interrupt Enable Set Register Section 4.24
0x01c640dc RCPPIIENCLRR Receive CPPI Interrupt Enable Clear Register Section 4.25
0x01c640e0 RBUFCNT0 Receive Buffer Count 0 Register Section 4.26
0x01c640e4 RBUFCNT1 Receive Buffer Count 1 Register Section 4.27
0x01c640e8 RBUFCNT2 Receive Buffer Count 2 Register Section 4.28
0x01c640ec RBUFCNT3 Receive Buffer Count 3 Register Section 4.29
- (Registers 0x01c6400f0 to 0x01c403ff to be done later)
0x01c40400 FADDR Function Address Register Section 4.45
0x01c40401 POWER Power Management Register Section 4.46
0x01c40402 INTRTX Interrupt Register for Endpoint 0 and for Endpoints 1 to 4 Transmit Section 4.47
0x01c40404 INTRRX Interrupt Register for Receive Endpoints 1 to 4 Section 4.48
0x01c40406 INTRTXE Interrupt enable register for INTRTX Section 4.49
0x01c40408 INTRRXE Interrupt Enable Register for INTRRX Section 4.50
0x01c4040a INTRUSB Interrupt Register for Common USB Interrupts Section 4.51
0x01c4040b INTRUSBE Interrupt Enable Register for INTRUSB Section 4.52
0x01c4040c FRAME Frame Number Register Section 4.53
0x01c4040e INDEX Index Register for Selecting the Endpoint Status and Control Registers Section 4.54
0x01c4040f TESTMODE Register to Enable the USB 2.0 Test Modes Section 4.55

ATA/CF

SPRUE21, page 33
Address Acronym Register Description Section
0x01c66000 BMICP Primary IDE Channel DMA Control Register Section 4.1
0x01c66002 BMISP Primary IDE Channel DMA Status Register Section 4.2
0x01c66004 BMIDTP Primary IDE Channel DMA Descriptor Table Pointer Register Section 4.3
0x01c66008 Reserved
0x01c6600c
0x01c66010
0x01c66014
0x01c66018
0x01c6601c
0x01c66020
0x01c66024
0x01c66028
0x01c6602c
0x01c66030
0x01c66034
0x01c66038
0x01c6603c
0x01c66040 IDETIMP Primary IDE Channel Timing Register Section 4.4
0x01c66047 IDESTAT IDE Controller Status Register Section 4.5
0x01c66048 UDMACTL Ultra-DMA Control Register Section 4.6
0x01c66050 MISCCTL Miscellaneous Control Register Section 4.7
0x01c66054 REGSTB Task File Register Strobe Timing Register Section 4.8
0x01c66058 REGRCVR Task File Register Recovery Timing Register Section 4.9
0x01c6605c DATSTB Data Register Access PIO Strobe Timing Register Section 4.10
0x01c66060 DATRCVR Data Register Access PIO Recovery Timing Register Section 4.11
0x01c66064 DMASTB Multiword DMA Strobe Timing Register Section 4.12
0x01c66068 DMARCVR Multiword DMA Recovery Timing Register Section 4.13
0x01c6606c UDMASTB Ultra-DMA Strobe Timing Register Section 4.14
0x01c66070 UDMATRP Ultra-DMA Ready-to-Pause Timing Register Section 4.15
0x01c66074 UDMATENV Ultra-DMA Timing Envelope Register Section 4.16
0x01c66078 IORDYTMP Primary IO Ready Timer Configuration Register Section 4.17

SPI

SPRUE32A, page 21
Address Acronym Register Description Section
0x01c66800 SPIGCR0 SPI global control register 0 Section 3.1
0x01c66804 SPIGCR1 SPI global control register 1 Section 3.2
0x01c66808 SPIINT SPI interrupt register Section 3.3
0x01c6680c SPILVL SPI interrupt level register Section 3.4
0x01c66810 SPIFLG SPI flag register Section 3.5
0x01c66814 SPIPC0 SPI pin control register Section 3.6
0x01c66818 Reserved
0x01c6681c SPIPC2 SPI pin control register 2 Section 3.7
0x01c66820 Reserved
0x01c66824
0x01c66828
0x01c6682c
0x01c66830
0x01c66834
0x01c66838
0x01c6683c SPIDAT1 SPI shift register Section 3.8
0x01c66840 SPIBUF SPI buffer register Section 3.9
0x01c66844 SPIEMU SPI emulation register Section 3.10
0x01c66848 SPIDELAY SPI delay register Section 3.11
0x01c6684c SPIDEF SPI default chip select register Section 3.12
0x01c66850 SPIFMT0 SPI data format register 0 Section 3.13
0x01c66854 SPIFMT1 SPI data format register 1 Section 3.13
0x01c66858 SPIFMT2 SPI data format register 2 Section 3.13
0x01c6685c SPIFMT3 SPI data format register 3 Section 3.13
0x01c66860 INTVECT0 SPI interrupt vector register 0 Section 3.14
0x01c66864 INTVECT1 SPI interrupt vector register 1 Section 3.15

GPIO

SPRUE25, page 16
Address Acronym Register Description Section
0x01c67000 PID Peripheral Identification Register Section 3.1
0x01c67008 BINTEN GPIO Interrupt Per-Bank Enable Register Section 3.2
0x01c6700c Reserved
0x01c67010 DIR01 GPIO Banks 0 and 1 Direction Register Section 3.3
0x01c67014 OUT_DATA01 GPIO Banks 0 and 1 Output Data Register Section 3.4
0x01c67018 SET_DATA01 GPIO Banks 0 and 1 Set Data Register Section 3.5
0x01c6701c CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register Section 3.6
0x01c67020 IN_DATA01 GPIO Banks 0 and 1 Input Data Register Section 3.7
0x01c67024 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register Section 3.8
0x01c67028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register Section 3.9
0x01c6702c SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register Section 3.10
0x01c67030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register Section 3.11
0x01c67034 INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register Section 3.12
0x01c67038 DIR23 GPIO Banks 2 and 3 Direction Register Section 3.3
0x01c6703c OUT_DATA23 GPIO Banks 2 and 3 Output Data Register Section 3.4
0x01c67040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register Section 3.5
0x01c67044 CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register Section 3.6
0x01c67048 IN_DATA23 GPIO Banks 2 and 3 Input Data Register Section 3.7
0x01c6704c SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register Section 3.8
0x01c67050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register Section 3.9
0x01c67054 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register Section 3.10
0x01c67058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register Section 3.11
0x01c6705c INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register Section 3.12
0x01c67060 DIR4 GPIO Bank 4 Direction Register Section 3.3
0x01c67064 OUT_DATA4 GPIO Bank 4 Output Data Register Section 3.4
0x01c67068 SET_DATA4 GPIO Bank 4 Set Data Register Section 3.5
0x01c6706c CLR_DATA4 GPIO Bank 4 Clear Data Register Section 3.6
0x01c67070 IN_DATA4 GPIO Bank 4 Input Data Register Section 3.7
0x01c67074 SET_RIS_TRIG4 GPIO Bank 4 Set Rising Edge Interrupt Register Section 3.8
0x01c67078 CLR_RIS_TRIG4 GPIO Bank 4 Clear Rising Edge Interrupt Register Section 3.9
0x01c6707c SET_FAL_TRIG4 GPIO Bank 4 Set Falling Edge Interrupt Register Section 3.10
0x01c67080 CLR_FAL_TRIG4 GPIO Bank 4 Clear Falling Edge Interrupt Register Section 3.11
0x01c67084 INTSTAT4 GPIO Bank 4 Interrupt Status Register Section 3.12

HPI

SPRUE97B, page 29
Address Acronym Register Description Section
0x01c67800 PID Peripheral Identification Register Section 3.1
0x01c67804 PWREMU_MGMT Power and Emulation Management Register Section 3.2
0x01c67808 Reserved
0x01c6780c
0x01c67810
0x01c67814
0x01c67818
0x01c6781c
0x01c67820
0x01c67824
0x01c67828
0x01c6782c
0x01c67830 HPIC Host Port Interface Control Register Section 3.3
0x01c67834 HPIAW Host Port Interface Write Address Register Section 3.4
0x01c67838 HPIAR Host Port Interface Read Address Register Section 3.5

VPSS

VPFE

CCDC

SPRUE38E, page 122
Address Acronym Register Description Section
0x01c70400 PID Peripheral revision and class information Section 6.1.1
0x01c70404 PCR Peripheral control register Section 6.1.2
0x01c70408 SYN_MODE SYNC and mode set register Section 6.1.3
0x01c7040c HD_VD_WID HD and VD signal width register Section 6.1.4
0x01c70410 PIX_LINES Number of pixels in a horizontal line and number of lines in a frame register Section 6.1.5
0x01c70414 HORZ_INFO Horizontal pixel information register Section 6.1.6
0x01c70418 VERT_START Vertical line - settings for the starting pixel register Section 6.1.7
0x01c7041c VERT_LINES Number of vertical lines register Section 6.1.8
0x01c70420 CULLING Culling information in horizontal and vertical directions register Section 6.1.9
0x01c70424 HSIZE_OFF Horizontal size register Section 6.1.10
0x01c70428 SDOFST SDRAM/DDRAM line offset register Section 6.1.11
0x01c7042c SDR_ADDR SDRAM address register Section 6.1.12
0x01c70430 CLAMP Optical black clamping settings register Section 6.1.13
0x01c70434 DCSUB DC clamp register Section 6.1.14
0x01c70438 COLPTN CCD color pattern register Section 6.1.15
0x01c7043c BLKCMP Black compensation register Section 6.1.16
0x01c70440 FPC Fault pixel correction Section 6.1.17
0x01c70444 FPC_ADDR Fault pixel Correction SDRAM Address Section 6.1.18
0x01c70448 VDINT VD interrupt timing register Section 6.1.19
0x01c7044c ALAW A-law setting register Section 6.1.20
0x01c70450 REC656IF REC656 interface register Section 6.1.21
0x01c70454 CCDCFG CCD configuration register Section 6.1.22
0x01c70458 FMTCFG Data reformatter/video port configuration register Section 6.1.23
0x01c7045c FMT_HORZ Data reformatter/video input interface horizontal information register Section 6.1.24
0x01c70460 FMT_VERT Data reformatter/video input interface vertical information register Section 6.1.25
0x01c70464 Reserved
0x01c70468
0x01c7046c
0x01c70470
0x01c70474
0x01c70478
0x01c7047c
0x01c70480
0x01c70484
0x01c70488
0x01c7048c
0x01c70490
0x01c70494 VP_OUT Video port output settings register Section 6.1.26

PREV

SPRUE38E, page 146
Address Acronym Register Description Section
0x01c70800 PID Peripheral revision and class information register Section 6.2.1
0x01c70804 PCR Peripheral control register Section 6.2.2
0x01c70808 HORZ_INFO Horizontal information/setup register Section 6.2.3
0x01c7080c VERT_INFO Vertical information/setup register Section 6.2.4
0x01c70810 RSDR_ADDR Read address from SDRAM register Section 6.2.5
0x01c70814 RADR_OFFSET Line offset for the read data register Section 6.2.5
0x01c70818 DSDR_ADDR Dark frame address from SDRAM register Section 6.2.7
0x01c7081c DRKF_OFFSET Line offset for the dark frame data register Section 6.2.8
0x01c70820 WSDR_ADDR Write address to SDRAM register Section 6.2.9
0x01c70824 WADD_OFFSET Line offset for the write data register Section 6.2.10
0x01c70828 AVE Input formatter/averager register Section 6.2.11
0x01c7082c HMED Horizontal median filter register Section 6.2.12
0x01c70830 NF Noise filter register Section 6.2.13
0x01c70834 WB_DGAIN White balance digital gain register Section 6.2.14
0x01c70838 WBGAIN White balance coefficients register Section 6.2.15
0x01c7083c WBSEL White balance coefficients selection register Section 6.2.16
0x01c70840 CFA CFA register Section 6.2.17
0x01c70844 BLKADJOFF Black adjustment offset register Section 6.2.18
0x01c70848 RGB_MAT1 RGB2RGB blending matrix coefficients register Section 6.2.19
0x01c7084c RGB_MAT2 RGB2RGB blending matrix coefficients register Section 6.2.20
0x01c70850 RGB_MAT3 RGB2RGB blending matrix coefficients register Section 6.2.21
0x01c70854 RGB_MAT4 RGB2RGB blending matrix coefficients register Section 6.2.22
0x01c70858 RGB_MAT5 RGB2RGB blending matrix coefficients register Section 6.2.23
0x01c7085c RGB_OFF1 RGB2RGB blending matrix offsets register Section 6.2.24
0x01c70860 RGB_OFF2 RGB2RGB blending matrix offsets register Section 6.2.25
0x01c70864 CSC0 Color space conversion coefficients register Section 6.2.26
0x01c70868 CSC1 Color space conversion coefficients register Section 6.2.27
0x01c7086c CSC2 Color space conversion coefficients register Section 6.2.28
0x01c70870 CSC_OFFSET Color space conversion offsets register Section 6.2.29
0x01c70874 CNT_BRT Contrast and brightness settings register Section 6.2.30
0x01c70878 CSUP Chrominance supression settings register Section 6.2.31
0x01c7087c SETUP_YC Maximum/minimum Y and C settings register Section 6.2.32
0x01c70880 SET_TBL_ADDRESS Setup table addresses register Section 6.2.33
0x01c70884 SET_TBL_DATA Setup table data register Section 6.2.34

RESZ

SPRUE38E, page 168
Address Acronym Register Description Section
0x01c70c00 PID Peripheral revision and class information register Section 6.3.1
0x01c70c04 PCR Peripheral control register Section 6.3.2
0x01c70c08 RSZ_CNT Resizer control bits register Section 6.3.3
0x01c70c0c OUT_SIZE Output width and height after resizing register Section 6.3.4
0x01c70c10 IN_START Input starting information register Section 6.3.5
0x01c70c14 IN_SIZE Input width and height before resizing register Section 6.3.6
0x01c70c18 SDR_INADD Input SDRAM address register Section 6.3.7
0x01c70c1c SDR_INOFF SDRAM offset for the input line register Section 6.3.8
0x01c70c20 SDR_OUTADD Output SDRAM address register Section 6.3.9
0x01c70c24 SDR_OUTOFF SDRAM offset for the output line register Section 6.3.10
0x01c70c28 HFILT10 Horizontal filter coefficients 1 and 0 register Section 6.3.11
0x01c70c2c HFILT32 Horizontal filter coefficients 3 and 2 register Section 6.3.11
0x01c70c30 HFILT54 Horizontal filter coefficients 5 and 4 register Section 6.3.11
0x01c70c34 HFILT76 Horizontal filter coefficients 7 and 6 register Section 6.3.11
0x01c70c38 HFILT98 Horizontal filter coefficients 9 and 8 register Section 6.3.11
0x01c70c3c HFILT1110 Horizontal filter coefficients 11 and 10 register Section 6.3.11
0x01c70c40 HFILT1312 Horizontal filter coefficients 13 and 12 register Section 6.3.11
0x01c70c44 HFILT1514 Horizontal filter coefficients 15 and 14 register Section 6.3.11
0x01c70c48 HFILT1716 Horizontal filter coefficients 17 and 16 register Section 6.3.11
0x01c70c4c HFILT1918 Horizontal filter coefficients 19 and 18 register Section 6.3.11
0x01c70c50 HFILT2120 Horizontal filter coefficients 21 and 20 register Section 6.3.11
0x01c70c54 HFILT2322 Horizontal filter coefficients 23 and 22 register Section 6.3.11
0x01c70c58 HFILT2524 Horizontal filter coefficients 25 and 24 register Section 6.3.11
0x01c70c5c HFILT2726 Horizontal filter coefficients 27 and 26 register Section 6.3.11
0x01c70c60 HFILT2928 Horizontal filter coefficients 29 and 28 register Section 6.3.11
0x01c70c64 HFILT3130 Horizontal filter coefficients 31 and 30 register Section 6.3.11
0x01c70c68 VFILT10 Vertical filter coefficients 1 and 0 register Section 6.3.12
0x01c70c6c VFILT32 Vertical filter coefficients 3 and 2 register Section 6.3.12
0x01c70c70 VFILT54 Vertical filter coefficients 5 and 4 register Section 6.3.12
0x01c70c74 VFILT76 Vertical filter coefficients 7 and 6 register Section 6.3.12
0x01c70c78 VFILT98 Vertical filter coefficients 9 and 8 register Section 6.3.12
0x01c70c7c VFILT1110 Vertical filter coefficients 11 and 10 register Section 6.3.12
0x01c70c80 VFILT1312 Vertical filter coefficients 13 and 12 register Section 6.3.12
0x01c70c84 VFILT1514 Vertical filter coefficients 15 and 14 register Section 6.3.12
0x01c70c88 VFILT1716 Vertical filter coefficients 17 and 16 register Section 6.3.12
0x01c70c8c VFILT1918 Vertical filter coefficients 19 and 18 register Section 6.3.12
0x01c70c90 VFILT2120 Vertical filter coefficients 21 and 20 register Section 6.3.12
0x01c70c94 VFILT2322 Vertical filter coefficients 23 and 22 register Section 6.3.12
0x01c70c98 VFILT2524 Vertical filter coefficients 25 and 24 register Section 6.3.12
0x01c70c9c VFILT2726 Vertical filter coefficients 27 and 26 register Section 6.3.12
0x01c70ca0 VFILT2928 Vertical filter coefficients 29 and 28 register Section 6.3.12
0x01c70ca4 VFILT3130 Vertical filter coefficients 31 and 30 register Section 6.3.12
0x01c70ca8 YENH Luminance enhancer register Section 6.3.13

HIST

SPRUE38E, page 178
Address Acronym Register Description Section
0x01c71000 PID Peripheral identification register Section 6.4.1
0x01c71004 PCR Peripheral control register Section 6.4.2
0x01c71008 HIST_CNT Histogram control register Section 6.4.3
0x01c7100c WB_GAIN White/channel balance settings register Section 6.4.4
0x01c71010 R0_HORZ Region 0 horizontal information register Section 6.4.5
0x01c71014 R0_VERT Region 0 vertical information register Section 6.4.6
0x01c71018 R1_HORZ Region 1 horizontal information register Section 6.4.5
0x01c7101c R1_VERT Region 1 vertical information register Section 6.4.6
0x01c71020 R2_HORZ Region 2 horizontal information register Section 6.4.5
0x01c71024 R2_VERT Region 2 vertical information register Section 6.4.6
0x01c71028 R3_HORZ Region 3 horizontal information register Section 6.4.5
0x01c7102c R3_VERT Region 3 vertical information register Section 6.4.6
0x01c71030 HIST_ADDR Histogram address register Section 6.4.7
0x01c71034 HIST_DATA Histogram data register Section 6.4.8
0x01c71038 RADD Read address register Section 6.4.9
0x01c7103c RADD_OFF Read address offset register Section 6.4.10
0x01c71040 H_V_INFO Horizontal/vertical information register Section 6.4.11

H3A

SPRUE38E, page 187
Address Acronym Register Description Section
0x01c71400 PID Peripheral revision and class information register Section 6.5.1
0x01c71404 PCR Peripheral control register Section 6.5.2
0x01c71408 AFPAX1 Setup for the AF engine paxel configuration register Section 6.5.3
0x01c7140c AFPAX2 Setup for the AF engine paxel configuration register Section 6.5.4
0x01c71410 AFPAXSTART Start position for AF engine paxels register Section 6.5.5
0x01c71414 AFIIRSH Start position for IIRSH register Section 6.5.6
0x01c71418 AFBUFST SDRAM/DDRAM start address for AF engine register Section 6.5.7
0x01c7141c AFCOEFF010 IIR filter coefficient data for SET 0 register Section 6.5.8
0x01c71420 AFCOEFF032 IIR filter coefficient data for SET 0 register Section 6.5.9
0x01c71424 AFCOEFF054 IIR filter coefficient data for SET 0 register Section 6.5.10
0x01c71428 AFCOEFF076 IIR filter coefficient data for SET 0 register Section 6.5.11
0x01c7142c AFCOEFF098 IIR filter coefficient data for SET 0 register Section 6.5.12
0x01c71430 AFCOEFF0010 IIR filter coefficient data for SET 0 register Section 6.5.13
0x01c71434 AFCOEFF110 IIR filter coefficient data for SET 1 register Section 6.5.14
0x01c71438 AFCOEFF132 IIR filter coefficient data for SET 1 register Section 6.5.15
0x01c7143c AFCOEFF154 IIR filter coefficient data for SET 1 register Section 6.5.16
0x01c71440 AFCOEFF176 IIR filter coefficient data for SET 1 register Section 6.5.17
0x01c71444 AFCOEFF198 IIR filter coefficient data for SET 1 register Section 6.5.18
0x01c71448 AFCOEFF1010 IIR filter coefficient data for SET 1 register Section 6.5.19
0x01c7144c AEWWIN1 Configuration for AE/AWB windows register Section 6.5.20
0x01c71450 AEWINSTART Start position for AE/AWB windows register Section 6.5.21
0x01c71454 AEWINBLK Start position and height for black line of AE/AWB windows register Section 6.5.22
0x01c71458 AEWSUBWIN Configuration for subsample data in AE/AWB window register Section 6.5.23

VPFE

SPRUE37C, page 126
Address Acronym Register Description Section
0x01c72780 PID Peripheral Revision and Class Information Register Section 6.1.1
0x01c72784 PCR Peripheral Control Register Section 6.1.2

VPBE

VENC

SPRUE37C, page 128
Address Acronym Register Description Section
0x01c72400 VMOD Video Mode Register Section 6.2.1
0x01c72404 VIDCTL Video Interface I/O Control Register Section 6.2.2
0x01c72408 VDPRO Video Data Processing Register Section 6.2.3
0x01c7240c SYNCCTL Sync Control Register Section 6.2.4
0x01c72410 HSPLS Horizontal Sync Pulse Width Register Section 6.2.5
0x01c72414 VSPLS Vertical Sync Pulse Width Register Section 6.2.6
0x01c72418 HINT Horizontal Interval Register Section 6.2.7
0x01c7241c HSTART Horizontal Valid Data Start Position Register Section 6.2.8
0x01c72420 HVALID Horizontal Data Valid Range Register Section 6.2.9
0x01c72424 VINT Vertical Interval Register Section 6.2.10
0x01c72428 VSTART Vertical Valid Data Start Position Register Section 6.2.11
0x01c7242c VVALID Vertical Data Valid Range Register Section 6.2.12
0x01c72430 HSDLY Horizontal Sync Delay Register Section 6.2.13
0x01c72434 VSDLY Vertical Sync Delay Register Section 6.2.14
0x01c72438 YCCTL YCbCr Control Register Section 6.2.15
0x01c7243c RGBCTL RGB Control Register Section 6.2.16
0x01c72440 RGBCLP RGB Level Clipping Register Section 6.2.17
0x01c72444 LINECTL Line Identification Control Register Section 6.2.18
0x01c72448 CULLLINE Culling Line Control Register Section 6.2.19
0x01c7244c LCDOUT LCD Output Signal Control Register Section 6.2.20
0x01c72450 BRTS Brightness Start Position Signal Control Register Section 6.2.21
0x01c72454 BRTW Brightness Width Signal Control Register Section 6.2.22
0x01c72458 ACCTL LCD_AC Signal Control Register Section 6.2.23
0x01c7245c PWMP PWM Start Position Signal Control Register Section 6.2.24
0x01c72460 PWMW PWM Width Signal Control Register Section 6.2.25
0x01c72464 DCLKCTL DCLK Control Register Section 6.2.26
0x01c72468 DCLKPTN0 DCLK Pattern 0 Register Section 6.2.27
0x01c7246c DCLKPTN1 DCLK Pattern 1 Register Section 6.2.27
0x01c72470 DCLKPTN2 DCLK Pattern 2 Register Section 6.2.27
0x01c72474 DCLKPTN3 DCLK Pattern 3 Register Section 6.2.27
0x01c72478 DCLKPTN0A DCLK Auxiliary Pattern 0 Register Section 6.2.28
0x01c7247c DCLKPTN1A DCLK Auxiliary Pattern 1 Register Section 6.2.28
0x01c72480 DCLKPTN2A DCLK Auxiliary Pattern 2 Register Section 6.2.28
0x01c72484 DCLKPTN3A DCLK Auxiliary Pattern 3 Register Section 6.2.28
0x01c72488 DCLKHS Horizontal DCLK Mask Start Register Section 6.2.29
0x01c7248c DCLKHSA Horizontal Auxiliary DCLK Mask Start Register Section 6.2.30
0x01c72490 DCLKHR Horizontal DCLK Mask Range Register Section 6.2.31
0x01c72494 DCLKVS Vertical DCLK Mask Start Register Section 6.2.32
0x01c72498 DCLKVR Vertical DCLK Mask Range Register Section 6.2.33
0x01c7249c CAPCTL Caption Control Register Section 6.2.34
0x01c724a0 CAPDO Caption Data Odd Field Register Section 6.2.35
0x01c724a4 CAPDE Caption Data Even Field Register Section 6.2.36
0x01c724a8 ATR0 Video Attribute Data 0 Register Section 6.2.37
0x01c724ac ATR1 Video Attribute Data 1 Register Section 6.2.38
0x01c724b0 ATR2 Video Attribute Data 2 Register Section 6.2.39
0x01c724b4 Reserved
0x01c724b8 VSTAT Video Status Register Section 6.2.40
0x01c724bc Reserved
0x01c724c0
0x01c724c4 DACTST DAC Test Register Section 6.2.41
0x01c724c8 YCOLVL YOUT and COUT Levels Register Section 6.2.42
0x01c724cc SCPROG Sub-Carrier Programming Register Section 6.2.43
0x01c724d0 Reserved
0x01c724d4
0x01c724d8
0x01c724dc CVBS Composite Mode Register Section 6.2.44
0x01c724e0 CMPNT Component Mode Register Section 6.2.45
0x01c724e4 ETMG0 CVBS Timing Control 0 Register Section 6.2.46
0x01c724e8 ETMG1 CVBS Timing Control 1 Register Section 6.2.47
0x01c724ec ETMG2 Component Timing Control 0 Register Section 6.2.48
0x01c724f0 ETMG3 Component Timing Control 1 Register Section 6.2.49
0x01c724f4 DACSEL DAC Output Select Register Section 6.2.50
0x01c724f8 Reserved
0x01c724fc
0x01c72500 ARGBX0 Analog RGB Matrix 0 Register Section 6.2.51
0x01c72504 ARGBX1 Analog RGB Matrix 1 Register Section 6.2.52
0x01c72508 ARGBX2 Analog RGB Matrix 2 Register Section 6.2.53
0x01c7250c ARGBX3 Analog RGB Matrix 3 Register Section 6.2.54
0x01c72510 ARGBX4 Analog RGB Matrix 4 Register Section 6.2.55
0x01c72514 DRGBX0 Digital RGB Matrix 0 Register Section 6.2.56
0x01c72518 DRGBX1 Digital RGB Matrix 1 Register Section 6.2.57
0x01c7251c DRGBX2 Digital RGB Matrix 2 Register Section 6.2.58
0x01c72520 DRGBX3 Digital RGB Matrix 3 Register Section 6.2.59
0x01c72524 DRGBX4 Digital RGB Matrix 4 Register Section 6.2.60
0x01c72528 VSTARTA Vertical Data Valid Start Position Register (for Even Field) Section 6.2.61
0x01c7252c OSDCLK0 OSD Clock Control 0 Register Section 6.2.62
0x01c72530 OSDCLK1 OSD Clock Control 1 Register Section 6.2.63
0x01c72534 HVLDCL0 Horizontal Valid Culling Control 0 Register Section 6.2.64
0x01c72538 HVLDCL1 Horizontal Valid Culling Control 1 Register Section 6.2.65
0x01c7253c OSDHADV OSD Horizontal Sync Advance Register Section 6.2.66
- (0x01c72540 - 0x01c725f0 Reserved)
0x01c725f4 VMISC VENC Miscellaneous Register Section 6.2.67

OSD

SPRUE37C, page 175
Address Acronym Register Description Section
0x1c72600 MODE OSD Mode Register Section 6.3.1
0x1c72604 VIDWINMD Video Window Mode Setup Register Section 6.3.2
0x1c72608 OSDWIN0MD OSD Window Mode Setup Register Section 6.3.3
0x1c7260c OSDWIN1MD OSD Window 1 Mode Setup Register Section 6.3.4
0x1c7260c OSDATRMD OSD Attribute Window Mode Setup Section 6.3.5
0x1c72610 RECTCUR Rectangular Cursor Setup Register Section 6.3.6
0x1c72614 Reserved
0x1c72618 VIDWIN0OFST Video Window 0 Offset Register Section 6.3.7
0x1c7261c VIDWIN1OFST Video Window 1 Offset Register Section 6.3.8
0x1c72620 OSDWIN0OFST OSD Window 0 Offset Register Section 6.3.9
0x1c72624 OSDWIN1OFST OSD Window 1 Offset Register Section 6.3.10
0x1c72628 Reserved
0x1c7262c VIDWIN0ADR Video Window 0 Address Register Section 6.3.11
0x1c72630 VIDWIN1ADR Video Window 1 Address Register Section 6.3.12
0x1c72634 Reserved
0x1c72638 OSDWIN0ADR OSD Window 0 Address Register Section 6.3.13
0x1c7263c OSDWIN1ADR OSD Window 1 Address Register Section 6.3.14
0x1c72640 BASEPX Base Pixel X Register Section 6.3.15
0x1c72644 BASEPY Base Pixel Y Register Section 6.3.16
0x1c72648 VIDWIN0XP Video Window 0 X-Position Register Section 6.3.17
0x1c7264c VIDWIN0YP Video Window 0 Y-Position Register Section 6.3.18
0x1c72650 VIDWIN0XL Video Window 0 X-Size Register Section 6.3.19
0x1c72654 VIDWIN0YL Video Window 0 Y-Size Register Section 6.3.20
0x1c72658 VIDWIN1XP Video Window 1 X-Position Register Section 6.3.21
0x1c7265c VIDWIN1YP Video Window 1 Y-Position Register Section 6.3.22
0x1c72660 VIDWIN1XL Video Window 1 X-Size Register Section 6.3.23
0x1c72664 VIDWIN1YL Video Window 1 Y-Size Register Section 6.3.24
0x1c72668 OSDWIN0XP OSD Bitmap Window 0 X-Position Register Section 6.3.25
0x1c7266c OSDWIN0YP OSD Bitmap Window 0 Y-Position Register Section 6.3.26
0x1c72670 OSDWIN0XL OSD Bitmap Window 0 X-Size Register Section 6.3.27
0x1c72674 OSDWIN0YL OSD Bitmap Window 0 Y-Size Register Section 6.3.28
0x1c72678 OSDWIN1XP OSD Bitmap Window 1 X-Position Register Section 6.3.29
0x1c7267c OSDWIN1YP OSD Bitmap Window 1 Y-Position Register Section 6.3.30
0x1c72680 OSDWIN1XL OSD Bitmap Window 1 X-Size Register Section 6.3.31
0x1c72684 OSDWIN1YL OSD Bitmap Window 1 Y-Size Register Section 6.3.32
0x1c72688 CURXP Rectangular Cursor Window X-Position Register Section 6.3.33
0x1c7268c CURYP Rectangular Cursor Window Y-Position Register Section 6.3.34
0x1c72690 CURXL Rectangular Cursor Window X-Size Register Section 6.3.35
0x1c72694 CURYL Rectangular Cursor Window Y-Size Register Section 6.3.36
0x1c72698 Reserved
0x1c7269c
0x1c726a0 W0BMP01 Window 0 Bitmap Value to Palette Map 0/1 Register Section 6.3.37
0x1c726a4 W0BMP23 Window 0 Bitmap Value to Palette Map 2/3 Register Section 6.3.38
0x1c726a8 W0BMP45 Window 0 Bitmap Value to Palette Map 4/5 Register Section 6.3.39
0x1c726ac W0BMP67 Window 0 Bitmap Value to Palette Map 6/7 Register Section 6.3.40
0x1c726b0 W0BMP89 Window 0 Bitmap Value to Palette Map 8/9 Register Section 6.3.41
0x1c726b4 W0BMPAB Window 0 Bitmap Value to Palette Map A/B Register Section 6.3.42
0x1c726b8 W0BMPCD Window 0 Bitmap Value to Palette Map C/D Register Section 6.3.43
0x1c726bc W0BMPEF Window 0 Bitmap Value to Palette Map E/F Register Section 6.3.44
0x1c726c0 W1BMP01 Window 1 Bitmap Value to Palette Map 0/1 Register Section 6.3.45
0x1c726c4 W1BMP23 Window 1 Bitmap Value to Palette Map 2/3 Register Section 6.3.46
0x1c726c8 W1BMP45 Window 1 Bitmap Value to Palette Map 4/5 Register Section 6.3.47
0x1c726cc W1BMP67 Window 1 Bitmap Value to Palette Map 6/7 Register Section 6.3.48
0x1c726d0 W1BMP89 Window 1 Bitmap Value to Palette Map 8/9 Register Section 6.3.49
0x1c726d4 W1BMPAB Window 1 Bitmap Value to Palette Map A/B Register Section 6.3.50
0x1c726d8 W1BMPCD Window 1 Bitmap Value to Palette Map C/D Register Section 6.3.51
0x1c726dc W1BMPEF Window 1 Bitmap Value to Palette Map E/F Register Section 6.3.52
0x1c726e0 Reserved
0x1c726e4
0x1c726e8 MISCCTL Miscellaneous Control Register Section 6.3.53
0x1c726ec CLUTRAMYCB CLUT RAMYCB Setup Register Section 6.3.54
0x1c726f0 CLUTRAMCR CLUT RAM Setup Register Section 6.3.55
0x1c726f4 TRANSPVAL Transparency Value Setup Register Section 6.3.56
0x1c726f8 Reserved
0x1c726fc PPVWIN0ADR Ping-Pong Video Window 0 Address Register Section 6.3.57

VPSS

SPRUE38E, page 202
Address Acronym Register Description Section
0x01c73400 PID VPSS Peripheral Revision and Class Information Section 7.1
0x01c73404 PCR VPSS Peripheral Control Register Section 7.2
0x01c73508 SDR_REQ_EXP SDRAM Non-Real-Time Read Request Expand Register Section 7.3

EMAC

SPRUE24A, page 69
Address Acronym Register Description Section
0x01c80000 TXIDVER Transmit Identification and Version Register Section 5.1
0x01c80004 TXCONTROL Transmit Control Register Section 5.2
0x01c80008 TXTEARDOWN Transmit Teardown Register Section 5.3
0x01c80010 RXIDVER Receive Identification and Version Register Section 5.4
0x01c80014 RXCONTROL Receive Control Register Section 5.5
0x01c80018 RXTEARDOWN Receive Teardown Register Section 5.6
- (0x01c8001c - 0x01c8007c Reserved)
0x01c80080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register Section 5.7
0x01c80084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register Section 5.8
0x01c80088 TXINTMASKSET Transmit Interrupt Mask Set Register Section 5.9
0x01c8008c TXINTMASKCLEAR Transmit Interrupt Clear Register Section 5.10
0x01c80090 MACINVECTOR MAC Input Vector Register Section 5.11
0x01c80094 Reserved
0x01c80098
0x01c8009c
0x01c800a0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register Section 5.12
0x01c800a4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register Section 5.13
0x01c800a8 RXINTMASKSET Receive Interrupt Mask Set Register Section 5.14
0x01c800ac RXINTMASKCLEAR Receive Interrupt Mask Clear Register Section 5.15
0x01c800b0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register Section 5.16
0x01c800b4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register Section 5.17
0x01c800b8 MACINTMASKSET MAC Interrupt Mask Set Register Section 5.18
0x01c800bc MACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 5.19
- (0x01c800c0 - 0x01c800fc Reserved)
0x01c80100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register Section 5.20
0x01c80104 RXUNICASTSET Receive Unicast Enable Set Register Section 5.21
0x01c80108 RXUNICASTCLEAR Receive Unicast Clear Register Section 5.22
0x01c8010c RXMAXLEN Receive Maximum Length Register Section 5.23
0x01c80110 RXBUFFEROFFSET Receive Buffer Offset Register Section 5.24
0x01c80114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register Section 5.25
0x01c80118 Reserved
0x01c8011c
0x01c80120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register Section 5.26
0x01c80124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register Section 5.26
0x01c80128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register Section 5.26
0x01c8012c RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register Section 5.26
0x01c80130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register Section 5.26
0x01c80134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register Section 5.26
0x01c80138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register Section 5.26
0x01c8013c RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register Section 5.26
0x01c80140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register Section 5.27
0x01c80144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register Section 5.27
0x01c80148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register Section 5.27
0x01c8014c RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register Section 5.27
0x01c80150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register Section 5.27
0x01c80154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register Section 5.27
0x01c80158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register Section 5.27
0x01c8015c RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.27
0x01c80160 MACCONTROL MAC Control Register Section 5.28
0x01c80164 MACSTATUS MAC Status Register Section 5.29
0x01c80168 EMCONTROL Emulation Control Register Section 5.30
0x01c8016c FIFOCONTROL FIFO Control Register Section 5.31
0x01c80170 MACCONFIG MAC Configuration Register Section 5.32
0x01c80174 SOFTRESET Soft Reset Register Section 5.33
- (0x01c80178 - 0x01c801cc Reserved)
0x01c801d0 MACSRCADDRLO MAC Source Address Low Bytes Register Section 5.34
0x01c801d4 MACSRCADDRHI MAC Source Address High Bytes Register Section 5.35
0x01c801d8 MACHASH1 MAC Hash Address Register 1 Section 5.36
0x01c801dc MACHASH2 MAC Hash Address Register 2 Section 5.37
0x01c801e0 BOFFTEST Back Off Test Register Section 5.38
0x01c801e4 TPACETEST Transmit Pacing Algorithm Test Register Section 5.39
0x01c801e8 RXPAUSE Receive Pause Timer Register Section 5.40
0x01c801ec TXPAUSE Transmit Pause Timer Register Section 5.41
0x01c801f0 Reserved
0x01c801f4
0x01c801f8
0x01c801fc
0x01c80200 RXGOODFRAMES Good Receive Frames Register Section 5.49.1
0x01c80204 RXBCASTFRAMES Broadcast Receive Frames Register Section 5.49.2
0x01c80208 RXMCASTFRAMES Multicast Receive Frames Register Section 5.49.3
0x01c8020c RXPAUSEFRAMES Pause Receive Frames Register Section 5.49.4
0x01c80210 RXCRCERRORS Receive CRC Errors Register Section 5.49.5
0x01c80214 RXALIGNCODEERRORS Receive Alignment/Code Errors Register Section 5.49.6
0x01c80218 RXOVERSIZED Receive Oversized Frames Register Section 5.49.7
0x01c8021c RXJABBER Receive Jabber Frames Register Section 5.49.8
0x01c80220 RXUNDERSIZED Receive Undersized Frames Register Section 5.49.9
0x01c80224 RXFRAGMENTS Receive Frame Fragments Register Section 5.49.10
0x01c80228 RXFILTERED Filtered Receive Frames Register Section 5.49.11
0x01c8022c RXQOSFILTERED Receive QOS Filtered Frames Register Section 5.49.12
0x01c80230 RXOCTETS Receive Octet Frames Register Section 5.49.13
0x01c80234 TXGOODFRAMES Good Transmit Frames Register Section 5.49.14
0x01c80238 TXBCASTFRAMES Broadcast Transmit Frames Register Section 5.49.15
0x01c8023c TXMCASTFRAMES Multicast Transmit Frames Register Section 5.49.16
0x01c80240 TXPAUSEFRAMES Pause Transmit Frames Register Section 5.49.17
0x01c80244 TXDEFERRED Deferred Transmit Frames Register Section 5.49.18
0x01c80248 TXCOLLISION Transmit Collision Frames Register Section 5.49.19
0x01c8024c TXSINGLECOLL Transmit Single Collision Frames Register Section 5.49.20
0x01c80250 TXMULTICOLL Transmit Multiple Collision Frames Register Section 5.49.21
0x01c80254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register Section 5.49.22
0x01c80258 TXLATECOLL Transmit Late Collision Frames Register Section 5.49.23
0x01c8025c TXUNDERRUN Transmit Underrun Error Register Section 5.49.24
0x01c80260 TXCARRIERSENSE Transmit Carrier Sense Errors Register Section 5.49.25
0x01c80264 TXOCTETS Transmit Octet Frames Register Section 5.49.26
0x01c80268 FRAME64 Transmit and Receive 64 Octet Frames Register Section 5.49.27
0x01c8026c FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register Section 5.49.28
0x01c80270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register Section 5.49.29
0x01c80274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register Section 5.49.30
0x01c80278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register Section 5.49.31
0x01c8027c FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Register Section 5.49.32
0x01c80280 NETOCTETS Network Octet Frames Register Section 5.49.33
0x01c80284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register Section 5.49.34
0x01c80288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 5.49.35
0x01c8028c RXDMAOVERRUNS Receive DMA Overruns Register Section 5.49.36
- (0x01c80290 - 0x01c804fc Reserved)
0x01c80500 MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching Section 5.42
0x01c80504 MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching Section 5.43
0x01c80508 MACINDEX MAC Index Register Section 5.44
- (0x01c8050c - 0x01c805fc Reserved)
0x01c80600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register Section 5.45
0x01c80604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register Section 5.45
0x01c80608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register Section 5.45
0x01c8060c TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register Section 5.45
0x01c80610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register Section 5.45
0x01c80614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register Section 5.45
0x01c80618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 5.45
0x01c8061c TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 5.45
0x01c80620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5.46
0x01c80624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section 5.46
0x01c80628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register Section 5.46
0x01c8062c RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register Section 5.46
0x01c80630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register Section 5.46
0x01c80634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register Section 5.46
0x01c80638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register Section 5.46
0x01c8063c RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register Section 5.46
0x01c80640 TX0CP Transmit Channel 0 Completion Pointer Register Section 5.47
0x01c80644 TX1CP Transmit Channel 1 Completion Pointer Register Section 5.47
0x01c80648 TX2CP Transmit Channel 2 Completion Pointer Register Section 5.47
0x01c8064c TX3CP Transmit Channel 3 Completion Pointer Register Section 5.47
0x01c80650 TX4CP Transmit Channel 4 Completion Pointer Register Section 5.47
0x01c80654 TX5CP Transmit Channel 5 Completion Pointer Register Section 5.47
0x01c80658 TX6CP Transmit Channel 6 Completion Pointer Register Section 5.47
0x01c8065c TX7CP Transmit Channel 7 Completion Pointer Register Section 5.47
0x01c80660 RX0CP Receive Channel 0 Completion Pointer Register Section 5.48
0x01c80664 RX1CP Receive Channel 1 Completion Pointer Register Section 5.48
0x01c80668 RX2CP Receive Channel 2 Completion Pointer Register Section 5.48
0x01c8066c RX3CP Receive Channel 3 Completion Pointer Register Section 5.48
0x01c80670 RX4CP Receive Channel 4 Completion Pointer Register Section 5.48
0x01c80674 RX5CP Receive Channel 5 Completion Pointer Register Section 5.48
0x01c80678 RX6CP Receive Channel 6 Completion Pointer Register Section 5.48
0x01c8067c RX7CP Receive Channel 7 Completion Pointer Register Section 5.48

EMAC CMR

SPRUE24A, page 54
Address Acronym Register Description Section
0x01c81004 EWCTL EMAC Control Module Interrupt Control Register Section 3.1
0x01c81008 EWINTTCNT EMAC Control Module Interrupt Timer Count Register Section 3.2

MDIO

SPRUE24A, page 56
Address Acronym Register Description Section
0x01c84000 VERSION MDIO Version Register Section 4.1
0x01c84004 CONTROL MDIO Control Register Section 4.2
0x01c84008 ALIVE PHY Alive Status register Section 4.3
0x01c8400c LINK PHY Link Status Register Section 4.4
0x01c84010 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register Section 4.5
0x01c84014 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register Section 4.6
0x01c84018 Reserved
0x01c8401c
0x01c84020 USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register Section 4.7
0x01c84024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register Section 4.8
0x01c84028 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register Section 4.9
0x01c8402c USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 4.10
0x01c84030 Reserved
0x01c84034
0x01c84038
0x01c8403c
0x01c84040
0x01c84044
0x01c84048
0x01c8404c
0x01c84050
0x01c84054
0x01c84058
0x01c8405c
0x01c84060
0x01c84064
0x01c84068
0x01c8406c
0x01c84070
0x01c84074
0x01c84078
0x01c8407c
0x01c84080 USERACCESS0 MDIO User Access Register 0 Section 4.11
0x01c84084 USERPHYSEL0 MDIO User PHY Select Register 0 Section 4.12
0x01c84088 USERACCESS1 MDIO User Access Register 1 Section 4.13
0x01c8408c USERPHYSEL1 MDIO User PHY Select Register 1 Section 4.14

EMIF

SPRUE20C, page 48
Address Acronym Register Description Section
0x01e00000 Reserved
0x01e00004 AWCCR Asynchronous Wait Cycle Configuration Register Section 4.1
0x01e00008 Reserved
0x01e0000c
0x01e00010 A1CR Asynchronous 1 Configuration Register (CS2 space) Section 4.2
0x01e00014 A2CR Asynchronous 2 Configuration Register (CS3 space) Section 4.2
0x01e00018 A3CR Asynchronous 3 Configuration Register (CS4 space) Section 4.2
0x01e0001c A4CR Asynchronous 4 Configuration Register (CS5 space) Section 4.2
0x01e00020 Reserved
0x01e00024
0x01e00028
0x01e0002c
0x01e00030
0x01e00034
0x01e00038
0x01e0003c
0x01e00040 EIRR EMIF Interrupt Raw Register Section 4.3
0x01e00044 EIMR EMIF Interrupt Mask Register Section 4.4
0x01e00048 EIMSR EMIF Interrupt Mask Set Register Section 4.5
0x01e0004c EIMCR EMIF Interrupt Mask Clear Register Section 4.6
0x01e00050 Reserved
0x01e00054
0x01e00058
0x01e0005c
0x01e00060 NANDFCR NAND Flash Control Register Section 4.7
0x01e00064 NANDFSR NAND Flash Status Register Section 4.8
0x01e00068 Reserved
0x01e0006c
0x01e00070 NANDF1ECC NAND Flash 1 ECC Register (CS2 Space) Section 4.9
0x01e00074 NANDF2ECC NAND Flash 2 ECC Register (CS3 Space) Section 4.9
0x01e00078 NANDF3ECC NAND Flash 3 ECC Register (CS4 Space) Section 4.9
0x01e0007c NANDF4ECC NAND Flash 4 ECC Register (CS5 Space) Section 4.9

VLYNQ

SPRUE36A, page 25
Address Acronym Register Description Section
0x01e01000 REVID Revision Register Section 3.1
0x01e01004 CTRL Control Register Section 3.2
0x01e01008 STAT Status Register Section 3.3
0x01e0100c INTPRI Interrupt Priority Vector Status/Clear Register Section 3.4
0x01e01010 INTSTATCLR Interrupt Status/Clear Register Section 3.5
0x01e01014 INTPENDSET Interrupt Pending/Set Register Section 3.6
0x01e01018 INTPTR Interrupt Pointer Register Section 3.7
0x01e0101c XAM Transmit Address Map Register Section 3.8
0x01e01020 RAMS1 Receive Address Map Size 1 Register Section 3.9
0x01e01024 RAMO1 Receive Address Map Offset 1 Register Section 3.10
0x01e01028 RAMS2 Receive Address Map Size 2 Register Section 3.11
0x01e0102c RAMO2 Receive Address Map Offset 2 Register Section 3.12
0x01e01030 RAMS3 Receive Address Map Size 3 Register Section 3.13
0x01e01034 RAMO3 Receive Address Map Offset 3 Register Section 3.14
0x01e01038 RAMS4 Receive Address Map Size 4 Register Section 3.15
0x01e0103c RAMO4 Receive Address Map Offset 4 Register Section 3.16
0x01e01040 CHIPVER Chip Version Register Section 3.17
0x01e01044 AUTNGO Auto Negotiation Register Section 3.18

ASP

SPRUE29B, page 44
Address Acronym Register Description Section
- RBR Receive buffer register -
- RSR Receive shift register -
- XSR Transmit shift register -
0x01e02000 DRR Data receive register Section 3.1
0x01e02004 DXR Data transmit register Section 3.2
0x01e02008 SPCR Serial port control register Section 3.3
0x01e0200c RCR Receive control register Section 3.4
0x01e02010 XCR Transmit control register Section 3.5
0x01e02014 SRGR Sample rate generator register Section 3.6
0x01e02018 Reserved
0x01e0201c
0x01e02020
0x01e02024 PCR Pin control register Section 3.7

MMC/SD/SDIO

SPRUE30D, page 40
Address Acronym Register Description Section
0x01e10000 MMCCTL MMC Control Register Section 4.1
0x01e10004 MMCCLK MMC Memory Clock Control Register Section 4.2
0x01e10008 MMCST0 MMC Status Register 0 Section 4.3
0x01e1000c MMCST1 MMC Status Register 1 Section 4.4
0x01e10010 MMCIM MMC Interrupt Mask Register Section 4.5
0x01e10014 MMCTOR MMC Response Time-Out Register Section 4.6
0x01e10018 MMCTOD MMC Data Read Time-Out Register Section 4.7
0x01e1001c MMCBLEN MMC Block Length Register Section 4.8
0x01e10020 MMCNBLK MMC Number of Blocks Register Section 4.9
0x01e10024 MMCNBLC MMC Number of Blocks Counter Register Section 4.10
0x01e10028 MMCDRR MMC Data Receive Register Section 4.11
0x01e1002c MMCDXR MMC Data Transmit Register Section 4.12
0x01e10030 MMCCMD MMC Command Register Section 4.13
0x01e10034 MMCARGHL MMC Argument Register Section 4.14
0x01e10038 MMCRSP01 MMC Response Register 0 and 1 Section 4.15
0x01e1003c MMCRSP23 MMC Response Register 2 and 3 Section 4.15
0x01e10040 MMCRSP45 MMC Response Register 4 and 5 Section 4.15
0x01e10044 MMCRSP67 MMC Response Register 6 and 7 Section 4.15
0x01e10048 MMCDRSP MMC Data Response Register Section 4.16
0x01e1004c Reserved
0x01e10050 MMCCIDX MMC Command Index Register Section 4.17
0x01e10054 Reserved
0x01e10058
0x01e1005c
0x01e10060
0x01e10064 SDIOCTL SDIO Control Register Section 4.18
0x01e10068 SDIOST0 SDIO Status Register 0 Section 4.19
0x01e1006c SDIOIEN SDIO Interrupt Enable Register Section 4.20
0x01e10070 SDIOIST SDIO Interrupt Status Register Section 4.21
0x01e10074 MMCFIFOCTL MMC FIFO Control Register Section 4.22

VLYNQ (Remote)

SPRUE36A, page 39
Address Acronym Register Description Section
0x0c000080 RREVID Remote Revision Register
0x0c000084 RCTRL Remote Control Register
0x0c000088 RSTAT Remote Status Register
0x0c00008c RINTPRI Remote Interrupt Priority Vector Status/Clear Register
0x0c000090 RINTSTATCLR Remote Interrupt Status/Clear Register
0x0c000094 RINTPENDSET Remote Interrupt Pending/Set Register
0x0c000098 RINTPTR Remote Interrupt Pointer Register
0x0c00009c RXAM Remote Transmit Address Map Register
0x0c0000a0 RRAMS1 Remote Receive Address Map Size 1 Register
0x0c0000a4 RRAMO1 Remote Receive Address Map Offset 1 Register
0x0c0000a8 RRAMS2 Remote Receive Address Map Size 2 Register
0x0c0000ac RRAMO2 Remote Receive Address Map Offset 2 Register
0x0c0000b0 RRAMS3 Remote Receive Address Map Size 3 Register
0x0c0000b4 RRAMO3 Remote Receive Address Map Offset 3 Register
0x0c0000b8 RRAMS4 Remote Receive Address Map Size 4 Register
0x0c0000bc RRAMO4 Remote Receive Address Map Offset 4 Register
0x0c0000c0 RCHIPVER Chip Version Register
0x0c0000c4 RAUTNGO Auto Negotiation Register
0x0c0000c8 RMANNGO Remote Manual Negotiation Register
0x0c0000cc RNGOSTAT Remote Negotiation Status Register
0x0c0000d0 Reserved
0x0c0000d4
0x0c0000d8
0x0c0000dc
0x0c0000e0 RINTVEC0 Remote Interrupt Vector 3-0 Register
0x0c0000e4 RINTVEC1 Remote Interrupt Vector 7-4 Register
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